library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity MUX_ANGLE is -- todo el ingles!!!
	port( C1 			: in std_logic;
		   C2			 	:	in std_logic;
		   OUTPUT 		: out std_logic_vector(8 downto 0)
	);
end MUX_ANGLE;
-- Multiplos de delta fi
--00 o 11 => 0
--01 => 1
--10 => -1

architecture mux of MUX_ANGLE is
begin
	process(C1,C2)
	begin
		 OUTPUT(0) <= C1 xor C2;
		 OUTPUT(8 downto 1) <= (8 downto 1 =>(C1 and not(C2)));
	end process;
end mux;

